MIS capacitor and method of formation

ABSTRACT

An MIS capacitor with low leakage and high capacitance is disclosed. A layer of hemispherical grained polysilicon (HSG) is formed as a lower electrode. Prior to the dielectric formation, the hemispherical grained polysilicon layer may be optionally subjected to a nitridization or anneal process. A dielectric layer of aluminum oxide (Al 2 O 3 ), or a composite stack of interleaved layers of aluminum oxide and other metal oxide dielectric materials, is fabricated over the hemispherical grained polysilicon layer and after the optional nitridization or anneal process. The dielectric layer of aluminum oxide (Al 2 O 3 ) or the aluminum oxide composite stack may be optionally subjected to a post-deposition treatment to further increase the capacitance and decrease the leakage current. A metal nitride upper electrode is formed over the dielectric layer or the composite stack by a deposition technique or by atomic layer deposition.

FIELD OF THE INVENTION

[0001] The present invention relates to the field of integrated circuitsand, in particular, to a novel method of forming capacitor structures.

BACKGROUND OF THE INVENTION

[0002] A dynamic random access memory (DRAM) cell typically comprises acharge storage capacitor coupled to an access device such as aMetal-Oxide-Semiconductor Field Effect Transistor (MOSFET). The MOSFETfunctions to apply or remove charge on the capacitor, thus affecting alogical state defined by the stored charge. The amount of charge storedon the capacitor is determined by the capacitance C=εε_(o) A/d, where εis the dielectric constant of the capacitor dielectric, ε_(o) is thevacuum permittivity, A is the electrode (or storage node) area, and d isthe interelectrode spacing. The conditions of DRAM operation, such asoperating voltage, leakage rate and refresh rate, will in generalmandate that a certain minimum charge be stored by the capacitor.

[0003] In the continuing trend to higher memory capacity, the packingdensity of storage cells must increase, yet each must maintain requiredcapacitance levels. This is a crucial demand of DRAM fabricationtechnologies if future generations of expanded memory array devices areto be successfully manufactured. Nevertheless, in the trend to highermemory capacity, the packing density of cell capacitors has increased atthe expense of available cell area. For example, the area allowed for asingle cell in a 64-Mbit DRAM is only about 1.4 μm². In such limitedareas, it is difficult to provide sufficient capacitance usingconventional stacked capacitor structures. Yet, design and operationalparameters determine the minimum charge required for reliable operationof the memory cell despite decreasing cell area.

[0004] Several techniques have been developed to increase the totalcharge capacity or the capacitance of the cell capacitor withoutsignificantly affecting the cell area.

[0005] For example, new capacitor dielectric materials with highdielectric constants have been introduced to replace conventionaldielectric materials such as silicon nitride. This way, thin films ofmaterials having a high dielectric constant, such as Ta₂O₅ (tantalumpentoxide), Barium Titanate (BT), Strontium Titanate (ST), LeadZirconium Titanate (PZT), or Bismuth Strontium Titanate (BST), have beenincreasingly utilized as the cell dielectric material of choice ofDRAMs. Although these materials have a high dielectric constant and lowleakage currents, there are some technical difficulties associated withthese materials.

[0006] One problem with incorporating these materials into current DRAMcell designs is their chemical reactivity with the polycrystallinesilicon (polysilicon or “poly”) that conventionally forms a capacitorelectrode of a metal-insulator-semiconductor (MIS) capacitor. Capacitorsmade of polysilicon-PZT/BST sandwiches undergo chemical and physicaldegradation with thermal processing. During the chemical vapordeposition (CVD) of PZT/BST, oxygen in the ambient tends to oxidize theelectrode material. The oxide is undesirable because it has a much lowerdielectric constant compared to that of PZT/BST, and adds in series tothe capacitance of the PZT/BST, thus drastically lowering the totalcapacitance of the capacitor. Thus, even a thin native oxide layerpresent on the electrode results in a large degradation in capacitance.

[0007] Accordingly, there is a need for a method of forming ametal-insulator-semiconductor (MIS) capacitor having increasedcapacitance per cell and low leakage, as well as a method of forming acapacitor structure that achieves high storage capacitance withoutincreasing the size of the capacitor. An MIS capacitor with increasedcapacitance and reduced leakage current is also needed.

BRIEF SUMMARY OF THE INVENTION

[0008] The present invention provides an MIS capacitor and a method offorming an MIS capacitor with low leakage and high capacitance.

[0009] The MIS capacitor of the present invention comprises a layer ofhemispherical grained polysilicon (HSG) as a lower capacitor electrode,which may be optionally nitridized or oxidized. A dielectric layercomprising aluminum oxide (Al₂O₃), or a dielectric composite stackcomprising one or more layers of Al₂O₃ interleaved with one or morelayers of other dielectric metal oxides, is provided over the layer ofhemispherical grained polysilicon (HSG). An upper electrode of a metalnitride layer is formed over the dielectric layer or the dielectriccomposite stack.

[0010] The present invention also provides a method of forming an MIScapacitor with reduced leakage current and high capacitance. A layer ofhemispherical grained polysilicon (HSG) is formed as a lower electrode.After its formation and prior to the dielectric formation, the layer ofhemispherical grained polysilicon (HSG) may be subsequently subjected toa nitridization or an anneal process to passivate the HSG surface andimprove the cell capacitance and the leakage. A dielectric layercomprising aluminum oxide (Al₂O₃), or a dielectric composite stackcomprising a plurality of interleaved layers of Al₂O₃ and otherdielectric oxides, is formed over the layer of hemispherical grainedpolysilicon (HSG) by atomic layer deposition (ALD), for example. Thedielectric layer or the dielectric composite stack is optionallysubjected to a post-dielectric deposition treatment, for example, anitridization or an anneal treatment, to further reduce leakage andincrease the dielectric stability. An upper electrode of metal nitridematerial is formed over the dielectric layer or the dielectric compositestack by a deposition process or by an atomic layer deposition (ALD)method.

[0011] The foregoing and other advantages and features of the inventionwill be better understood from the following detailed description of theinvention, which is provided in connection with the accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012]FIG. 1 is a schematic cross-sectional view of a portion of amemory DRAM device, in which an MIS capacitor will be fabricatedaccording to a method of the present invention.

[0013]FIG. 2 is a schematic cross-sectional view of the FIG. 1 device ata stage of processing subsequent to that shown in FIG. 1.

[0014]FIG. 3 is a schematic cross-sectional view of the FIG. 1 device ata stage of processing subsequent to that shown in FIG. 2.

[0015]FIG. 4 is a schematic cross-sectional view of the FIG. 1 device ata stage of processing subsequent to that shown in FIG. 3.

[0016]FIG. 5 is a schematic cross-sectional view of the FIG. 1 device ata stage of processing subsequent to that shown in FIG. 4.

[0017]FIG. 6 is a schematic cross-sectional view of the FIG. 1 device ata stage of processing subsequent to that shown in FIG. 5.

[0018]FIG. 7 is a schematic cross-sectional view of the FIG. 1 device ata stage of processing subsequent to that shown in FIG. 6.

[0019]FIG. 8 is a schematic cross-sectional view of the FIG. 1 device ata stage of processing subsequent to that shown in FIG. 7.

[0020]FIG. 9 is a schematic cross-sectional view of the FIG. 1 device ata stage of processing subsequent to that shown in FIG. 8.

[0021]FIG. 10 is a schematic cross-sectional view of the FIG. 1 deviceat a stage of processing subsequent to that shown in FIG. 9.

[0022]FIG. 11 is a schematic cross-sectional view of the FIG. 1 deviceat a stage of processing subsequent to that shown in FIG. 10.

[0023]FIG. 12 is a schematic cross-sectional view of the FIG. 1 deviceat a stage of processing subsequent to that shown in FIG. 11.

[0024]FIG. 13 is a schematic cross-sectional view of the FIG. 1 deviceat a stage of processing subsequent to that shown in FIG. 11 and inaccordance with another embodiment of the present invention.

[0025]FIG. 14 is a schematic cross-sectional view of the FIG. 1 deviceat a stage of processing subsequent to that shown in FIG. 11 and inaccordance with an embodiment of the present invention.

[0026]FIG. 15 is a schematic cross-sectional view of the FIG. 1 deviceat a stage of processing subsequent to that shown in FIG. 11 and inaccordance with an embodiment of the present invention.

[0027]FIG. 16 is a schematic cross-sectional view of the FIG. 1 deviceat a stage of processing subsequent to that shown in FIG. 11.

[0028]FIG. 17 is a schematic cross-sectional view of the FIG. 1 deviceat a stage of processing subsequent to that shown in FIG. 12.

[0029]FIG. 18 is a schematic cross-sectional view of the FIG. 1 deviceat a stage of processing subsequent to that shown in FIG. 17.

[0030]FIG. 19 is an illustration of a computer system having a memorydevice with an MIS capacitor constructed in accordance with the presentinvention.

[0031]FIG. 20 is a graph illustrating data measurements for the leakagecurrent and the capacitance of five MIS capacitors, of which three arefabricated according to embodiments of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0032] In the following detailed description, reference is made tovarious specific embodiments in which the invention may be practiced.These embodiments are described with sufficient detail to enable thoseskilled in the art to practice the invention, and it is to be understoodthat other embodiments may be employed, and that structural, logical,and electrical changes may be made.

[0033] The term “substrate” used in the following description mayinclude any semiconductor-based structure that has a semiconductorsurface. Structure must be understood to include silicon, silicon-oninsulator (SOI), silicon-on sapphire (SOS), doped and undopedsemiconductors, epitaxial layers of silicon supported by a basesemiconductor foundation, and other semiconductor structures. Thesemiconductor also need not be silicon-based. The semiconductor could besilicon-germanium, germanium, or gallium arsenide. When reference ismade to a substrate in the following description, previous process stepsmay have been utilized to form regions or junctions in or on the basesemiconductor or foundation.

[0034] The term “metal” is intended to include not only elemental metal,but metal with other trace metals or in various alloyed combinationswith other metals as known in the semiconductor art, as long as suchalloy remains electrically conductive. Similarly, the term “aluminumoxide” includes not only elemental aluminum oxide, but aluminum oxidewith other trace materials or in various alloyed combinations as knownin the semiconductor art, as long as such alloy or combination retainsthe physical and electrical properties of aluminum oxide.

[0035] Referring now to the drawings, where like elements are designatedby like reference numerals, FIG. 1 depicts a memory cell constructionfor a DRAM at an intermediate stage of the fabrication, in which a pairof memory cells having respective access transistors are formed on asubstrate 12. The FIG. 1 structure includes the substrate 12 having awell 13, which is typically doped to a predetermined conductivity, forexample p-type or n-type depending on whether NMOS or PMOS transistorswill be formed therein. The structure further includes field oxideregions 14, conventional doped active areas 16 for use as source/drainregions, and a pair of gate stacks 30, all formed according towell-known semiconductor processing techniques. The gate stacks 30include a gate oxide layer 18, a conductive gate layer 20, such aspolysilicon or polysilicon covered by a silicide, nitride spacers 32 anda nitride cap 22.

[0036] Above the gate oxide region 18, the polysilicon gates 20, and theprotective nitride regions 22, 32, a first insulating layer 24 (FIG. 1)is disposed. Insulating layer 24 could be formed of silicon oxide,borophosphosilicate glass (BPSG), borosilicate glass (BSG), orphosphosilicate glass (PSG), among others.

[0037] Reference is now made to FIG. 2, which for simplicity illustratesonly a lateral portion, for example, the right side portion of FIG. 1.This is a region where a contact plug and an overlying MIS capacitorstructure 100 (FIG. 18) fabricated according to exemplary embodiments ofthe present invention will be formed. To create a contact opening 40(FIG. 3) into the substrate 12 through the first insulating layer 24, aphotoresist material 26 (FIG. 2) is deposited and patterned usingconventional photolithography steps. After patterning, an initialopening 27 (FIG. 2) is formed in the photoresist layer 26 for subsequentoxide etching. The first insulating layer 24 of FIG. 2 is then etched,to form a contact opening 40, and the photoresist layer 26 is removed,as shown in FIG. 3. The contact opening 40 extends to the source/drainregion 16 provided in the well 13 of the substrate 12.

[0038] Next, contact opening 40 (FIG. 3) is filled with a conductivematerial, such as doped polysilicon, that is planarized down to or nearthe planar surface of the first insulating layer 24, to form apolysilicon plug or filler 50, as illustrated in FIG. 4. The polysiliconplug 50 is then anisotropically etched until its top surface is recessedbelow the planar surface of the first insulating layer 24, so that abarrier layer 52 (FIG. 5) can be deposited and planarized, as shown inFIG. 5. The barrier layer 52, preferably of titanium (Ti), is formed onthe polysilicon plug 50 by CVD, PVD, sputtering or evaporation, to athickness of about 60 to about 200 Angstroms. The titanium barrier layer52 will form titanium silicide (TiSi₂) during a later high temperatureanneal.

[0039] Although the present invention is described with reference to theformation of an MIS capacitor 100 (FIG. 18) over the polysilicon plug50, including the barrier layer 52, it must be understood that theexistence of the barrier layer 52 is optional, and that the presentinvention also applies to capacitors formed over polysilicon plugswithout protective barrier layer 52.

[0040]FIG. 6 illustrates the deposition of a second insulating layer 25,which could be, for example, a silicon oxide, borophosphosilicate glass(BPSG), borosilicate glass (BSG), phosphosilicate glass (PSG), ortetraethylortho silicate (TEOS). The second insulating layer 25 isdeposited over the barrier layer 52 and the first insulating layer 24.Again, using the same fabrication technique as that used for theformation of contact opening 40 (FIG. 3) through the first insulatinglayer 24, a capacitor opening 41 (FIG. 7) is formed through the secondinsulating layer 25.

[0041] Subsequent to the formation of capacitor opening 41 of FIG. 7, alayer 60 of semiconductive material is formed inside the capacitoropening 41 and over the upper surface of the insulating layer 25, asillustrated in FIG. 8. Layer 60 of semiconductive material may comprisehemispherical grained polysilicon (HSG), silica, silicon, germanium, orany alloy of silica or germanium. Preferably, layer 60 of semiconductivematerial is formed of hemispherical grained polysilicon (HSG). If HSG isemployed, the layer 60 may be formed by first depositing a layer ofin-situ doped polysilicon followed by a deposition of undoped HSG.Subsequent heating inherent in wafer processing could effectivelyconductively dope the overlying HSG layer. Alternatively, the HSG layer60 may be provided by in-situ arsenic doping of an entire HSG layer, orby depositing amorphous silicon and then using a selective seed followedby an annealing process. The HSG layer 60 is in electrical contact withthe previously formed conductive plug 50 over the active area 16.Although the present invention will be described below with reference tolayer 60 of semiconductive material as to the HSG layer 60, it must beunderstood that this embodiment is only exemplary and the invention isnot limited to it.

[0042] Referring now to FIG. 9, the capacitor opening 41 of FIG. 8 isnext filled with a photoresist material 61 by, for example, spin coatingat room temperature and then solidifying it. The photoresist material61, which can be any photochemical resin used in the semiconductorindustry, as well as the horizontal portions of the HSG layer 60 locatedabove the second insulating layer 25, are then planarized by CMP down toor near the planar surface of the upper surface of the second insulatinglayer 25 to form a photoresist plug 63 (FIG. 10). The photoresist plug63 acts as a protective barrier for portions of the HSG layer 60 whichcontact the vertical walls of the contact opening 41, as well as for thehorizontal portion of the HSG layer 60 which is situated above thepolysilicon plug 50.

[0043] Next, the chemically mechanically polished photoresist plug 63(FIG. 10) is removed by using conventional techniques, such as ashing orplasma etching, to form the structure of FIG. 11. Upon removal of thephotoresist plug 63, the HSG layer 60 may be optionally cleaned with adilute cleaning solution, for example, a dilute solution of hydrofluoricacid (HF) with a 10:1 volumetric ratio of water to 49% HF, to remove anyimpurities and/or material residue present on the HSG layer 60.

[0044] Subsequent to the removal of the photoresist plug 63 and of theoptional cleaning step described above, the HSG layer 60 may be furthersubjected to an etching solution, for example, a hydrofluoric acid (HF)etching solution, to form an etched HSG layer 62, as illustrated in FIG.11. The etching solution removes any native oxide formed over the HSGlayer 60 and further enlarges the openings of the HSG grains andactivates the HSG grains of the HSG layer 60. This way, the etched HSGlayer 62 with activated HSG grains allows the subsequently depositeddielectric material to achieve good conformal properties with the etchedHSG layer 62 and better step coverage.

[0045] According to an embodiment of the present invention, the etchedHSG layer 62 (FIG. 11) may be optionally subjected to a nitridizing oran oxidizing ambient to densify the etched HSG layer 62 and, therefore,to decrease the leakage and increase the cell capacitance. Thenitridizing or oxidizing ambient of the present invention alsopassivates the surface of the etched HSG layer 62 to prevent theunwanted diffusion and reactions between the etched HSG layer 62 and theoxide material of the subsequently deposited dielectric material. Inthis manner, the passivated surface of the etched HSG layer 62, which isa result of the nitridizing or oxidizing ambient, prevents any ionpermeation in the etched HSG layer 62 such as oxygen ions from thesubsequently deposited aluminum oxide layer 70 (FIG. 12) into the etchedHSG layer 62. The passivation of the etched HSG layer 62 also eliminatesthe need for high temperature anneals which are typically required forthe formation of a conventional oxide dielectric layer as part of acapacitor stack on an HSG layer.

[0046] As such, the etched HSG layer 62 may be subjected to anitridizing ambient, for example, a rapid thermal nitridation (RTN)process, a remote plasma nitridization (RPN) process, an in-situ remoteRF nitridization, or a combination of these processes. If an RPN processis employed, the substrate 12 may be placed in a reaction chamber andthe etched HSG layer 62 may be subsequently exposed to anitrogen-containing plasma formed from N₂ and H₂ within the reactionchamber. An exemplary nitrogen-containing plasma mixture comprises byvolume from about 10% to about 80% of N₂ and from about 20% to about 90%H₂, at a temperature of from about 100° C. to about 800° C., morepreferably of about 400° C. to about 600° C. The nitrogen-containingplasma mixture may further comprise argon (Ar) or another inert gas,typically in a percentage of about 0.01% to about 40% argon or inertgas, by volume.

[0047] Alternatively, the etched HSG layer 62 may be subjected to ananneal treatment, such as an in-situ PH₃ anneal at about 750° C. and forabout 30 minutes. A nitrogen (N₂) or ammonia (NH₃) plasma anneal, or anyother nitrogen source plasma anneal, may be also employed with orwithout an inert gas for annealing the etched HSG layer 62 to confer abetter interface between the etched HSG layer 62 and the subsequentlyformed metal oxide dielectric layer.

[0048] If a rapid thermal nitridization (RTN) process is used forpassivating the surface of the etched HSG layer 62 and, consequently,for improving the cell capacitance and reducing the leakage, the rapidthermal nitridization (RTN) process may take place at temperaturesranging from about 600° C. to about 1200° C., more preferably betweenabout 600° C. to about 800° C., for a time period ranging from about 5seconds to about 60 seconds, preferably from about 20 seconds to about60 seconds.

[0049] In another embodiment of the present invention, the etched HSGlayer 62 may be subjected to an oxidizing ambient, for example, a remoteplasma oxidation (RPO) ambient using an oxygen (O₂) or ozone (O₃)source, with or without ultraviolet light. A wet oxidizing chemistry maybe also used to induce the passivation of the surface of the etched HSGlayer 62.

[0050] According to yet another embodiment of the present invention, theetched HSG layer 62 may be subjected to both an anneal treatment, suchas an in-situ PH₃ anneal, and a rapid thermal nitridization (RTN)process. For example, the etched HSG layer 62 may be first subjected toan in-situ PH₃ anneal at about 750° C. and for about 30 minutes followedby an RTN treatment at about 800° C. for about 60 seconds. According toanother embodiment of the present invention and to further improve thecapacitance and decrease the leakage, a cleaning step may be performedbefore the anneal treatment. For example, a dilute cleaning solutionsuch as a dilute hydrofluoric acid (HF) solution having a 10:1volumetric ratio of water to 49% HF may be used before the in-situ PH₃anneal.

[0051] According to yet another embodiment of the invention, a cleaningstep may be performed after the PH₃ treatment and before the rapidthermal nitridization (RTN) process. For example, a dilute cleaningsolution such as a dilute hydrofluoric acid (HF) solution having a 10:1volumetric ratio of water to 49% HF may be used after the in-situ PH₃anneal and before the nitridization step outlined above. To furtherimprove the capacitance and decrease the leakage, the etched HSG layer62 may be also subjected to a first cleaning step before the PH₃treatment, and to a second cleaning step after the PH₃ treatment andbefore the RTN anneal. The first and second cleaning steps may employthe same or different cleaning solutions.

[0052] Referring now to FIG. 12, after the processing of the etched HSGlayer 62, a dielectric layer 70 is formed over the etched HSG layer 62and the top surface of the second insulating layer 25. According to apreferred embodiment of the invention, the dielectric layer 70 is formedof aluminum oxide (Al₂O₃) material and reference to the dielectric layer70 will be made in this application as to the aluminum oxide (Al₂O₃)layer 70. Aluminum oxide is preferred over other dielectric metal oxidematerials, such as tantalum oxide (Ta₂O₅), for example, because aluminumoxide is more stable than these dielectric oxides at high processingtemperatures. In addition, unlike the majority of dielectric oxidesincluding Ta₂O₅ which require oxidation anneal temperatures higher than700° C. and about several hours of oxidation, aluminum oxide structuresdo not require an oxidation anneal after Al₂O₃ deposition. As known inthe art, metal oxide dielectric films such as Ta₂O₅ films requireoxidation anneals after their deposition. The oxidation anneal alsoforms an oxynitride layer which grows at the HSG/Ta₂O₅ interface, forexample. Unfortunately, although the oxynitride layer formed at theHSG/Ta₂O₅ interface decreases the leakage current significantly, it alsoreduces the effective permittivity and, therefore, the overallcapacitance of the MIS structure. As aluminum oxide structures do notrequire an oxidation anneal after Al₂O₃ deposition, the formation of alow permittivity oxynitride layer at the HSG/Al₂O₃ dielectric interfaceis eliminated and the capacitance of the MIS structure is not affectednegatively.

[0053] The Al₂O₃ dielectric layer 70 (FIG. 12) may be formed by adeposition technique, for example chemical vapor deposition (CVD),metalorganic chemical vapor deposition (MOCVD) or sputtering, amongothers, to a thickness of about 10 Angstroms to about 500 Angstroms,more preferably of about 25 Angstroms to about 100 Angstroms.

[0054] In yet another exemplary embodiment of the present invention, theAl₂O₃ dielectric layer 70 of FIG. 12 is formed by an atomic layerdeposition (ALD) technique to further improve the quality of thedielectric film. According to this embodiment, a first species ofaluminum precursor, such as an aluminum source precursor, for exampletrimethyl-aluminum (TMA), is first deposited over the surface of theetched HSG layer 62 (FIG. 11) and the second insulating layer 25 as afirst monolayer. A second species of oxygen precursor, which may be anoxygen (O₂), an ozone (O₃) or water (H₂O) source, for example, is nextapplied over the monolayer of the first species of precursor. The secondspecies of precursor reacts with the monolayer of the first species ofprecursor to form an aluminum oxide (Al₂O₃) layer.

[0055] Each of the Al₂O₃ layers of the first and second species ofprecursors is provided on the surface of the etched HSG layer 62 andover the upper surface of the second insulating layer 25 by firstpulsing the first species (also called first precursor gas) and then thesecond species (also called second precursor gas) into the region of thesurface of the etched HSG layer 62 and of the second insulating layer25. The sequence of depositing the monolayers of the first and secondspecies of precursors can be repeated cycle after cycle and as often asneeded, until a desired thickness is reached for the Al₂O₃ dielectriclayer 70. Between each of the precursor gas pulses, the process regionis exhausted and a pulse of purge gas is injected. In any event, thethickness of the Al₂O₃ dielectric layer 70 formed by the ALD processoutlined above is in the range of about 10 Angstroms to about 100Angstroms, more preferably of about 25 Angstroms to about 50 Angstroms.

[0056] FIGS. 13-15 illustrate exemplary embodiments of the presentinvention, according to which at least one aluminum-containinginterfacial layer is formed between the Al₂O₃ dielectric layer 70 andthe etched HSG layer 62, and/or between the Al₂O₃ dielectric layer 70and the subsequently formed upper electrode. For example, FIG. 13illustrates an interfacial Al—O—Si layer 72 formed at the etched HSGlayer 62/Al₂O₃ dielectric layer 70 interface. FIG. 14 illustrates aninterfacial Al-metal-O—N layer 74 formed at the Al₂O₃ dielectric layer70/upper electrode interface. FIG. 15 illustrates both an interfacialAl—O—Si layer 72 and an interfacial Al-metal-O—N layer 74 formed at therespective interfaces of the Al₂O₃ dielectric layer 70 with the etchedHSG layer 62 and with the upper electrode to be formed.

[0057] The incorporation of silicon atoms in the aluminum-containinginterfacial Al—O—Si layer 72 confers a smooth and continuous interfacebetween the polysilicon of the etched HSG layer 62 and the dielectricmaterial of the Al₂O₃ dielectric layer 70. Similarly, the incorporationof metal atoms in the aluminum-containing interfacial Al-metal-O—N layer74 also confers a smooth and continuous interface between the dielectricmaterial of the Al₂O₃ dielectric layer 70 and the conductive material ofthe metal nitride upper electrode.

[0058] The interfacial Al—O—Si layer 72 of FIGS. 13 and 15 may be formedto a thickness of about 5 Angstroms to about 50 Angstroms, by adeposition process, for example chemical vapor deposition (CVD), usingan aluminum source, an oxygen source and a silicon source as precursors.For example, the Al—O—Si layer 72 may be formed using trimethyl-aluminum(TMA) as the aluminum source precursor, ozone (O₃) as the oxygen sourceprecursor, and silane as the silicon source precursor, at a temperatureof about 100° C. to about 800° C., more preferably of about 400° C.

[0059] According to a preferred embodiment of the invention, theinterfacial Al—O—Si layer 72 of FIGS. 13 and 15 may be formed in-situduring the formation of the Al₂O₃ dielectric layer 70 of FIG. 12. Forexample, the interfacial Al—O—Si layer 72 (FIGS. 13, 15) may be formedin-situ during the atomic layer deposition of the Al₂O₃ dielectric layer70, using a similar sequence of steps described above for the formationof the Al₂O₃ dielectric layer 70. According to the ALD embodiment, afirst species of aluminum precursor, such as an aluminum sourceprecursor, for example trimethyl-aluminum (TMA), is first deposited overthe surface of the etched HSG layer 62 (FIG. 11) and the secondinsulating layer 25 as a first monolayer. A second species of oxygenprecursor, which may be an oxygen (O₂) or an ozone (O₃) source, or water(H₂O) for example, is next applied over the monolayer of the firstspecies of precursor. The second species of precursor reacts with themonolayer of the first species of precursor to form an aluminum oxide(Al₂O₃) layer. A third species of silicon precursor, which may be silaneor a multiple-order silane such as di-silane or tri-silane, is nextapplied over the monolayer of the first and second species of precursorto form an Al—O—Si layer. The sequence of depositing the monolayers ofthe first, second and third species of precursors is repeated cycleafter cycle and as often as needed, until the thickness for theinterfacial Al—O—Si layer 72 (FIGS. 13, 15) is of about 5 Angstroms toabout 50 Angstroms.

[0060] The interfacial Al-metal-O—N layer 74 of FIGS. 14 and 15 formedat the Al₂O₃ dielectric layer 70/upper electrode interface may be alsoformed to a thickness of about 5 Angstroms to about 50 Angstroms, byeither a deposition technique or by atomic layer deposition. The metalcomponent of the interfacial Al-metal-O—N layer 74 is similar to themetal component of the metal nitride material which will form the upperelectrode. For example, if the upper electrode to be formed comprisestitanium nitride (TiN) material, then the interfacial Al-metal-O—N layer74 is an interfacial Al—Ti—O—N layer 74. Similarly, if the upperelectrode to be formed comprises tungsten nitride (WNx) material, thenthe interfacial Al-metal-ON layer 74 is an interfacial Al—W—O—N layer74. Although, for simplicity, reference to the Al-metal-O—N layer 74will be made below as to the Al—Ti—O—N layer 74, it must be understoodthat the invention is not limited to this embodiment and the inventioncontemplates the formation of various interfacial Al-metal-O—N layers74, according to the metal of choice of the metal nitride upperelectrode to be formed.

[0061] According to one embodiment of the invention, the Al—Ti—O—N layer74 (FIGS. 14, 15) may be formed to a thickness of about 5 Angstroms toabout 100 Angstroms, by a deposition process, for example atomic layerdeposition (ALD), using an aluminum source, a titanium source, an oxygensource and a nitrogen source as precursors. For example, the Al—Ti—O—Nlayer 74 may be formed using trimethyl-aluminum (TMA) as the aluminumsource precursor, titanium tetrachloride (TiCl₄) as the titanium source,ozone (O₃) as the oxygen source precursor, and ammonia (NH₃) source asthe nitrogen source precursor, at a temperature of about 100° C. toabout 800° C., more preferably of about 400° C.

[0062] According to a preferred embodiment of the invention, theinterfacial Al—Ti—O—N layer 74 of FIGS. 14 and 15 may be formed in-situduring the formation of the Al₂O₃ dielectric layer 70 (FIG. 12) and ofthe interfacial Al—O—Si layer 72 (FIGS. 13, 15). For example, theinterfacial Al—Ti—O—N layer 74 (FIGS. 14, 15) may be formed in-situduring the atomic layer deposition of the Al₂O₃ dielectric layer 70 andof the Al—Ti—O—N layer 74, using a similar sequence of steps describedabove for the formation of the Al₂O₃ dielectric layer 70 (FIG. 12). Assuch, monolayers of aluminum, titanium, oxygen and nitrogen speciesprecursors, are sequentially deposited cycle after cycle and as often asneeded, until the thickness for the interfacial Al—Ti—O—N layer 74 ofFIGS. 14 and 15 is of about 5 Angstroms to about 100 Angstroms.

[0063]FIG. 16 illustrates yet another embodiment of the presentinvention, according to which a dielectric Al₂O₃ composite stack layer80 is formed over the etched HSG layer 62 and the upper surface of thesecond insulating layer 25. The Al₂O₃ composite stack layer 80 maycomprise one or more layers of aluminum oxide interleaved with one ormore layers of other dielectric materials such as tantalum oxide,(Ta₂O₅), zirconium oxide (ZrO₂), hafnium oxide (HfO), ahafnium-aluminum-oxygen alloy (Hf—Al—O), or a lanthanum-aluminum-oxygenalloy (La—Al—O), among others.

[0064] For example, the composite stack layer 80 may be an in-situdeposited composite stack of Al₂O₃/Ta₂O₄ (aluminum oxide/tantalumoxide), or an in-situ deposited composite stack of Al₂O₃/Ta₂O₅/Al₂O₃(aluminum oxide/tantalum oxide/aluminum oxide), or a composite stackcomprising a plurality of interleaved and alternating layers ofAl₂O₃(aluminum oxide) and Ta₂O₅ (tantalum oxide). Since the permittivityof bulk Al₂O₃ (aluminum oxide) is lower than that of Ta₂O₅ (tantalumoxide), the addition of Ta₂O₅ (tantalum oxide) to a composite stackcomprising Al₂O₃ (aluminum oxide) significantly increases the overallpermittivity of the composite stack. Also, since Al₂O₃ has a dielectricconstant (of about 9-12) lower than the dielectric constant of Ta₂O₅ (ofabout 18-45), the addition of Ta₂O₅ further increases the totaldielectric constant of the Al₂O₃/Ta₂O₅ (aluminum oxide/tantalum oxide)or Al₂O₃/Ta₂O₅/Al₂O₃ (aluminum oxide/tantalum oxide/aluminum oxide)stacks and thus the total capacitance. In addition, a smooth HSG/Al₂O₃interface is achieved without any need for an additional interfaciallayer. In any event, the total thickness of the Al₂O₃ composite stacklayer 80 is of about 10 Angstroms to about 500 Angstroms, morepreferably of about 25 Angstroms to about 100 Angstroms.

[0065] The Al₂O₃ composite stack layer 80 may be further formed as aplurality of interleaved layers of Al₂O₃ and other dielectric oxides,for example, zirconium oxide (ZrO₂), hafnium oxide (HfO), ahafnium-aluminum-oxygen alloy (Hf—Al—O), or a lanthanum-aluminum-oxygenalloy (La—Al—O), among others. The Al₂O₃ composite stack layer 80 may bealso formed as a plurality of interleaved layers of Al₂O₃ and acombination of dielectric metal oxides, for example, a combination ofany of zirconium oxide (ZrO₂), hafnium oxide (HfO), ahafnium-aluminum-oxygen alloy (Hf—Al—O), or a lanthanum-aluminum-oxygenalloy (La—Al—O), among others. In such cases, each of the aluminum oxideand of the dielectric metal oxides may be formed by either a depositiontechnique, for example chemical vapor deposition (CVD) or plasmaenhanced chemical vapor deposition (PECVD), or by atomic layerdeposition (ALD), the processing details of which were described abovewith reference to the formation of the Al₂O₃ dielectric layer 70 of FIG.12. Each of the above-mentioned layers or plurality of interleavedlayers of the Al₂O₃ composite stack layer 80 may be formed in-situduring the formation of the aluminum oxide layer, for example, via ALD.

[0066] Subsequent to the formation of the Al₂O₃ dielectric layer 70(FIG. 12) or of the Al₂O₃ composite stack layer 80 (FIG. 16), thedielectric material may be further subjected to a post-Al₂O₃ depositiontreatment to further increase the stack stability and the stackcapacitance without degrading the leakage current. The post-Al₂O₃deposition treatment of the present invention replaces the conventionalpost-oxidation anneal, also known in the art as reoxidation, whichconventional dielectric oxides must undergo after their initialformation to significantly reduce the leakage current. As known in theart, dielectric oxides formed over a lower capacitor electrode haveoxygen (O₂) vacancies, the presence of which significantly affects theleakage current. To decrease the number of unwanted oxygen vacancies,the dielectric oxide is subjected to a reoxidation treatment which,although significantly decreasing the leakage current, also adverselyaffects the physical and electrical properties of the dielectric oxideand of the underlying polysilicon material, particularly as a result ofthe high oxidation temperatures. As described in more detail below withreference to FIG. 20, the formation of a 55 Angstroms Al₂O₃ dielectriclayer which undergoes a post-Al₂O₃ deposition confers acceptable leakagevalues without the conventional reoxidation treatment required fordielectric oxide materials.

[0067] Accordingly, as part of the post-Al₂O₃ deposition treatment forincreasing the stack stability and the stack capacitance withoutdegrading the leakage current, the Al₂O₃ dielectric layer 70 (FIG. 12)or the Al₂O₃ composite stack layer 80 (FIG. 16) may be subjected to amild surface nitridization process. This way, the dielectric layers 70,80 may be exposed to a nitridizing ambient under an RTN treatment fromabout 500° C. to about 900° C. for about 60 seconds. Alternatively, theAl₂O₃ dielectric layer 70 or the Al₂O₃ composite stack layer 80 may beexposed to a nitrogen-containing plasma formed from N₂ and H₂ within thereaction chamber. An exemplary nitrogen-containing plasma mixturecomprises by volume from about 10% to about 80% of N₂ and from about 20%to about 90% H₂, at a temperature of from about 100° C. to about 800°C., more preferably of about 400° C. to about 600° C. Thenitrogen-containing plasma mixture may further comprise argon (Ar) oranother inert gas, typically in a percentage of about 0.01% to about 40%argon or inert gas, by volume.

[0068] Referring now to FIG. 17, after the processing of the dielectriclayer is completed, a metal nitride layer 90 is formed as an uppercapacitor electrode 90 to complete the formation of the MIS capacitor100 (FIG. 18). Although the completion of the formation of the MIScapacitor 100 (FIG. 18) is explained below with reference to an uppercapacitor electrode formed over the Al₂O₃ dielectric layer 70 (FIG. 12),it must be understood that this embodiment is only exemplary.Accordingly, the present invention also contemplates the formation of anupper electrode over other Al₂O₃ dielectric structures formed accordingto embodiments of the present invention, for example the Al₂O₃dielectric layer 70 with the interfacial layers 72, 74 (FIGS. 13-15), orthe Al₂O₃ composite stack layer 80 (FIG. 16).

[0069] As illustrated in FIG. 17, the metal nitride layer 90 is formedover the Al₂O₃ dielectric layer 70 of FIG. 12 to a thickness of about 10Angstroms to about 1,000 Angstroms, more preferably of about 50Angstroms to about 250 Angstroms. The metal nitride layer 90 (FIG. 17)may be formed, for example, of titanium nitride (TiN) material which isan extremely hard material that is almost chemically inert (although itdissolves readily in hydrofluoric acid) and has excellent conductiveproperties. Titanium nitride also has a high melting point (about 3000°C.), which makes it unaffected by high processing temperatures and bymost reagents.

[0070] According to an embodiment of the present invention, the titaniumnitride layer 90 may be formed by a chemical vapor deposition (CVD)process using a metal source and a nitrogen source as precursors, at atemperature of about 500° C. to about 800° C., more preferably of about600° C. For example, the titanium nitride layer 90 may be formed using anitrogen source, such as an ammonia (NH₃) source, and a titanium sourceprecursor containing chlorine (Cl), such as TiCl₄ (titaniumtetrachloride), (C₅H₅)₂TiCl₂ [bis(cyclopentadienyl)titanium dichloride]or (C₅H₅)TiCl₃ (cyclopentadienyltitanium trichloride), among others.Alternatively, the titanium nitride layer 90 may be formed by alow-temperature chemical vapor deposition (CVD) process by adding(CH₃)HNNH₂ (methylhydrazine) to a titanium source containing chlorine(Cl), for example TiCl₄ (titanium tetrachloride). A metalorganicprecursor such as TiN[CH₂(CH₃)₂]₄ (tetrakis diethylamino titanium orTDEAT) or Ti[N(CH₃)₂]₄ (tetrakis dimethylamino titanium or TDMAT) may bealso used with a nitrogen source precursor to form the titanium nitridelayer 90 of FIG. 17.

[0071] According to yet another embodiment of the present invention, thetitanium nitride layer 90 (FIG. 17) may be formed by an atomic layerdeposition (ALD) process. Because the ALD process takes place at lowtemperatures, the low ALD temperatures prevent the degradation of theAl₂O₃ dielectric layer 70 during the ALD processing steps. The low ALDtemperatures also prevent the formation of additional oxygen vacanciesin the aluminum oxide material, which typically occur as a result ofhigh processing temperatures.

[0072] If ALD processing is employed, a first species of precursor,which may be a titanium source precursor containing chlorine (Cl), suchas TiCl₄ (titanium tertachloride) for example, is first deposited overthe surface of the dielectric layer 70 (FIG. 12) as a first monolayer. Asecond species of precursor, which may be an ammonia (NH₃) source, forexample, is next applied over the monolayer of the first species ofprecursor. The second species of precursor reacts with the monolayer ofthe first species of precursor to form a titanium nitride (TiN) layer.Each of the TiN layers of the first and second species of precursors areprovided on the surface of the dielectric layer 70 by first pulsing thefirst species (also called first precursor gas) and then the secondspecies (also called second precursor gas) into the region of thesurface of the dielectric layer 70. The sequence of depositing themonolayers of the first and second species of precursors can be repeatedcycle after cycle and as often as needed, until a desired thickness isreached for the titanium nitride (TiN) layer 90. Between each of theprecursor gas pulses, the process region is exhausted and a pulse ofpurge gas is injected. The thickness of the titanium nitride layer 90formed by the ALD process outlined above is in the range of about 10Angstroms to about 250 Angstroms, more preferably of about 100 Angstromsto about 200 Angstroms.

[0073] According to another embodiment of the present invention, themetal nitride layer 90 is formed of boron-doped titanium nitride (TiBN)material having a boron doping concentration of from about 0.01% toabout 30% (atomic percentage). Incorporation of boron into a titaniumnitride (TiN) film may be achieved by exposing the titanium nitride filmto B₂H₆ at a temperature of from about 200° C. to about 600° C., at apressure of from about 1 Torr to about 20 Torr, and for a period of timeof about 10 seconds to about 60 minutes to convert the titanium nitridefilm to the boron-doped titanium nitride layer 90 (FIG. 17).Alternatively, the incorporation of boron into a titanium nitride (TiN)film may be achieved by exposing the titanium nitride film to B₂H₆ andfurther to ultraviolet (UV) light, at a temperature of from about 200°C. to about 600° C., at a pressure of from about 1 Torr to about 20Torr, and for a period of time of about 10 seconds to about 60 minutes.Any wavelength in the ultraviolet range may be used for exposing theB₂H₆ and further incorporating the boron into the titanium nitridematerial. The boron-doped titanium nitride layer 90 (FIG. 17) may bealso formed by a chemical vapor deposition (CVD) process using a TiCl₄(titanium tetrachloride) source precursor, a B₂H₆ boron source and anammonia (NH₃) source at a temperature of about 600° C. to about 800° C.

[0074] According to yet another embodiment of the present invention, themetal nitride layer 90 (FIG. 17) may be formed of tungsten nitride(WN_(x)) material by a chemical vapor deposition (CVD) process using atungsten metal source and a nitrogen source as precursors. For example,the tungsten nitride layer 90 may be formed using a nitrogen source,such as an ammonia (NH₃) source, and a tungsten source precursor such astungsten hexafluoride (WF₆), at a temperature of about 300° C. to about500° C., more preferably of about 400° C.

[0075] According to yet another embodiment of the present invention, thetungsten nitride (WN_(x)) layer 90 (FIG. 17) may be formed by an atomiclayer deposition (ALD) process, as described above with reference to theformation of the ALD-formed titanium nitride (TiN) layer 90. For this, afirst species of precursor which may be a tungsten source precursorcontaining fluorine (F), such as tungsten hexafluoride (WF₆) forexample, is first deposited over the initial surface of the Al₂O₃dielectric layer 70 (FIG. 12) as a first monolayer. A second species ofprecursor, which may be a nitrogen (N₂) or an ammonia (NH₃) source, forexample, is next applied over the monolayer of the first species ofprecursor. The second species of precursor reacts with the monolayer ofthe first species of precursor to form a tungsten nitride (WN_(x))layer. Each of the WN_(v) layers of the first and second species ofprecursors is provided on the surface of the Al₂O₃ dielectric layer 70by first pulsing the first species and then the second species into theregion of the surface of the Al₂O₃ dielectric layer 70. As explainedabove, the sequence of depositing the monolayers of the first and secondspecies of precursors can be repeated cycle after cycle and as often asneeded, until a desired thickness is reached for the tungsten nitride(WN_(x)) layer 90. Preferably, the thickness of the tungsten nitridelayer 90 formed by the ALD process outlined above is in the range ofabout 10 Angstroms to about 250 Angstroms, more preferably of about 100Angstroms to about 200 Angstroms.

[0076]FIG. 18 illustrates the Al₂O₃ dielectric layer 70 and the metalnitride layer 90 patterned by a dry etch process, for example, tocomplete the formation of the MIS capacitor 100 having an uppercapacitor electrode formed of metal nitride material. To this end,further well-known processing steps to create a functional memory cellcontaining the MIS capacitor 100 may now be carried out.

[0077] A typical processor-based system 400 is illustrated in FIG. 19.The processor-based system 400 includes a memory circuit 448, forexample a DRAM memory, a SRAM memory, a Multi Chip Module (MCM), or amemory module containing one or more DRAM memory devices, at least onehaving at least one MIS capacitor, such as the MIS capacitor 100 (FIG.18) formed in accordance with the present invention. A processor system,which may be a computer system, generally comprises a central processingunit (CPU) 444, such as a microprocessor, a digital signal processor, orother programmable digital logic devices, which communicates with aninput/output (I/O) device 446 over a bus 452. The memory 448communicates with the CPU 444 for data exchange over bus 452 directly orthough a memory controller.

[0078] Examples of the implementation of the present invention will nowbe described with reference to FIG. 20. In each of the five sets ofexperiments which will be described in more detail below, the leakagecurrents of one control capacitor and four MIS capacitors, of whichthree were fabricated according to methods of the present invention,were measured and recorded. More specifically, two sets of measurementswere run for a control capacitor and for one MIS capacitor formedaccording to embodiments of the prior art, and three sets ofmeasurements were run for three MIS capacitors fabricated according tovarious embodiments of the present invention. The data from each set ofmeasurements was recorded and illustrated in FIG. 20.

[0079] First Set of Experiments

[0080] Under a first set of experiments, an ONO capacitor was formed ona semiconductor wafer according to an embodiment of the prior art as acontrol capacitor. The control ONO capacitor was fabricated with a lowerelectrode of HSG of about 400 Angstroms thick, a silicon nitride (Si₃N₄)dielectric layer of about 50 Angstroms thick, and an upper electrode ofpolysilicon of about 200 Angstroms thick. The HSG lower electrode, theSi₃N₄ dielectric layer and the polysilicon upper electrode were formedby chemical vapor deposition (CVD) at a temperature of about 600° C.

[0081] A first group of measurements for the capacitance and leakagecurrent of the control ONO capacitor described above was conducted fromvarious die locations across the wafer. The capacitance measurementswere conducted at 1 kHz and zero (0) bias, and the corresponding leakagecurrent measurements were conducted at 1.5 V DC bias and at about 85° C.The distribution of the leakage current vs. capacitance measurements forthe control ONO capacitor was recorded as region A in FIG. 20. Asillustrated in FIG. 20, for capacitance values of about 22 to 29 fF/cellcorresponding to the region A, the leakage current values are within 0.5to 2.0 fA/cell.

[0082] Second Set of Experiments

[0083] Under a second set of experiments, a Ta₂Os MIS capacitor wasformed on a semiconductor wafer according to another embodiment of theprior art. The Ta₂O₅ MIS capacitor was fabricated with a lower electrodeof HSG of about 400 Angstroms thick, a Ta₂O₅ dielectric layer of about40 Angstroms thick, and an upper electrode of titanium nitride (TiN) ofabout 200 Angstroms thick. The HSG lower electrode was formed bychemical vapor deposition (CVD) at a temperature of about 600° C. TheTa₂O₅ dielectric layer was also formed by chemical vapor deposition(CVD) at a temperature of about 475° C., while the titanium nitrideupper electrode was formed by chemical vapor deposition (CVD) at atemperature of about 600° C.

[0084] A second group of measurements for the capacitance and leakagecurrent of the Ta₂O₅ MIS capacitor described above was conducted fromvarious die locations across the wafer. The capacitance measurementswere conducted at 1 kHz and zero (0) bias, and the corresponding leakagecurrent measurements were conducted at 1.5 V DC bias and at about 85° C.The distribution of the leakage current vs. capacitance measurements forthe Ta₂O₅ MIS capacitor was recorded as region B in FIG. 20. Forcapacitance values of about 27 to 33 fF/cell corresponding to the regionB of FIG. 20, the leakage current values are within 0.5 to 3.0 fA/cell.

[0085] Third Set of Experiments

[0086] Under a third set of experiments, a first Al₂O₃ MIS capacitor wasformed on a semiconductor wafer according to a first embodiment of thepresent invention. The first Al₂O₃ MIS capacitor was fabricated with alower electrode of CVD hemispherical grained polysilicon of about 400Angstroms thick, an ALD Al₂O₃ dielectric layer of about 55 Angstromsthick, and an upper electrode of CVD titanium nitride of about 200Angstroms thick.

[0087] The ALD Al₂O₃ dielectric layer of the first Al₂O₃ MIS capacitorwas formed by atomic layer deposition using trimetyl-aluminum (TMA) asan aluminum source precursor and water. The titanium nitride upperelectrode was formed by chemical vapor deposition, employing TiCl₄(titanium tetrachloride) as precursor and ammonia (NH₃) as nitrogensource.

[0088] A third group of measurements for the capacitance and leakagecurrent of the first Al₂O₃ MIS capacitor described above was conductedfrom various die locations across the wafer. The capacitancemeasurements were conducted at 1 kHz and zero (0) bias, and thecorresponding leakage current measurements were conducted at 1.5 V DCbias and at about 85° C. The distribution of the leakage current vs.capacitance measurements for the first Al₂O₃ MIS capacitor was recordedas region C in FIG. 20. As illustrated in FIG. 20, for capacitancevalues of about 31 to 35 fF/cell corresponding to the region C, theleakage current values are within 0.4 to 2.0 fA/cell.

[0089] Fourth Set of Experiments

[0090] Under a fourth set of experiments, a second Al₂O₃ MIS capacitorwas formed on a semiconductor wafer according to a second embodiment ofthe present invention. The second Al₂O₃ MIS capacitor was fabricatedwith a lower electrode of CVD deposited hemispherical grainedpolysilicon of about 400 Angstroms thick, an ALD Al₂O₃ dielectric layerof about 55 Angstroms thick subjected to a post-Al₂O₃ depositiontreatment, and an upper electrode of CVD titanium nitride of about 200Angstroms thick.

[0091] The ALD Al₂O₃ dielectric layer of the second Al₂O₃ MIS capacitorwas formed by atomic layer deposition using trimetyl-aluminum (TMA) asan aluminum source precursor and water. The titanium nitride upperelectrode was formed by chemical vapor deposition, employing TiCl₄(titanium tetrachloride) as precursor and ammonia (NH₃) as a nitrogensource.

[0092] Prior to the formation of the ALD Al₂O₃ dielectric layer, thelower HSG electrode of the second Al₂O₃ MIS capacitor was subjected tothe following sequence of treatments: (1) a dilute hydrofluoric acid(HF) solution having a 10:1 volumetric ratio of water to 49% HF; (2) anin-situ PH₃ anneal at about 750° C. and for about 30 minutes; (3) adilute hydrofluoric acid (HF) solution having a 10:1 volumetric ratio ofwater to 49% HF; and (4) an RTN treatment at about 800° C. for about 60seconds in a nitrogen atmosphere.

[0093] A fourth group of measurements for the capacitance and leakagecurrent of the second Al₂O₃ MIS capacitor described above was conductedfrom various die locations across the wafer. The capacitancemeasurements were conducted at 1 kHz and zero (0) bias, and thecorresponding leakage current measurements were conducted at 1.5 V DCbias and at about 85° C. The distribution of the leakage current vs.capacitance measurements for the second Al₂O₃ MIS capacitor was recordedas region D in FIG. 20. For capacitance values of about 35 to 38 fF/cellcorresponding to the region D of FIG. 20, the leakage current values arewithin 0.5 to 3.0 fA/cell.

[0094] Fifth Set of Experiments

[0095] Under a fifth set of experiments, a third Al₂O₃ MIS capacitor wasformed on a semiconductor wafer according to a third embodiment of thepresent invention. The third Al₂O₃ MIS capacitor was fabricated with alower electrode of CVD deposited hemispherical grained polysilicon ofabout 400 Angstroms thick, an ALD Al₂O₃ dielectric layer of about 50Angstroms thick and subjected to a reoxidation treatment, and an upperelectrode of CVD titanium nitride of about 200 Angstroms thick.

[0096] The ALD Al₂O₃ dielectric layer of the third Al₂O₃ MIS capacitorwas formed by atomic layer deposition using trimethyl-aluminum (TMA) asan aluminum source precursor and water. Subsequent to its formation, theALD Al₂O₃ dielectric layer of the third Al₂O₃ MIS capacitor wassubjected to a post-deposition oxidation treatment. This way, the ALDAl₂O₃ dielectric layer underwent an oxidizing ambient under an ozonetreatment at about 475° C. for about 3 minutes. The titanium nitrideupper electrode was formed by chemical vapor deposition, employing TiCl₄as precursor and ammonia (NH₃) as a nitrogen source.

[0097] A fifth group of measurements for the capacitance and leakagecurrent of the third Al₂O₃ MIS capacitor described above was conductedfrom various die locations across the wafer. The capacitancemeasurements were conducted at 1 kHz and zero (0) bias, and thecorresponding leakage current measurements were conducted at 1.5 V DCbias and at about 85° C. The distribution of the leakage current vs.capacitance measurements for the third Al₂O₃ MIS capacitor was recordedas region E in FIG. 20. As illustrated in FIG. 20, for capacitancevalues of about 20 to 24 fF/cell corresponding to the region E, theleakage current values are within 0.1 to 0.4 fA/cell.

[0098] The results of the five sets of experiments detailed abovedemonstrate that the leakage current of an MIS capacitor fabricatedaccording to various embodiments of the present invention issubstantially decreased when the ALD Al₂O₃ dielectric layer is subjectedto a reoxidation treatment, such as the ozone reoxidation at about 475°C. for about 3 minutes explained above with reference to the fifth groupof measurements. This is exemplified by region E of FIG. 20, accordingto which the leakage current values for the third Al₂O₃ MIS capacitorfall between 0.1 to 0.4 fA/cell. However, the capacitance valuescorresponding to region E of FIG. 20 are also unacceptably low comparedto the capacitance values of the other four capacitors and theircorresponding regions A, B, C and D of FIG. 20.

[0099] The results of the five sets of experiments also demonstrate thatsubjecting the HSG lower electrode to a PH₃ anneal and an RTN treatmentbefore the formation of the ALD Al₂O₃ dielectric layer substantiallyincreases the capacitance values. FIG. 20 shows that the highestcapacitance values among all MIS capacitors correspond to region D ofthe second Al₂O₃ MIS capacitor. The capacitance values of the secondAl₂O₃ MIS capacitor, which fall between 35 to 38 fF/cell (region D ofFIG. 20), are higher than the capacitance values of all other fourregions A, B, C, and E corresponding to the other four capacitors.

[0100] Although the exemplary embodiments of the present invention havebeen described with reference to the formation of one MIS capacitor 100(FIG. 18), the invention also contemplates the formation of a pluralityof such capacitors, as desired in a DRAM memory array. In addition, theinvention contemplates the fabrication of an MIS capacitor, such as theMIS capacitor 100 of FIG. 18, on an integrated circuit substrate whichmay include other capacitor structures, for example, conventionalcontainer capacitors, MIM or SIS capacitors, among others.

[0101] In addition, although the formation of the MIS capacitor 100(FIG. 18) has been described with reference to the formation of theupper capacitor electrode 90 formed over the Al₂O₃ dielectric layer 70(FIG. 12), the invention also contemplates the formation of an MIScapacitor comprising an upper capacitor electrode formed over the Al₂O₃composite stack layer 80 (FIG. 16), which as described above may be, forexample, an in-situ deposited composite stack of Al₂O₃/Ta₂O₅/Al₂O₃(aluminum oxide/tantalum oxide/aluminum oxide), or over the Al₂O₃dielectric layer 70 with at least one of the interfacial layers 72, 74(FIGS. 13-15). Further, although Al₂O₃ (aluminum oxide) is the preferreddielectric material for the dielectric layer 70 (FIG. 12), the inventionis not limited to aluminum oxide. Accordingly, the invention alsocontemplates the use of other dielectric materials which can form stablecomposite stacks with other oxide dielectric materials, such as tantalumoxide, (Ta₂O₅), zirconium oxide (ZrO₂), hafnium oxide (HfO), ahafnium-aluminum-oxygen alloy (Hf—Al—O), or a lanthanum-aluminum-oxygenalloy (La—Al—O), among others. The invention further contemplates theuse of dielectric materials which are oxides and/or oxide combinationsof scandium (Sc), yttrium (Y), lanthanum (La), titanium (Ti), zirconium(Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta) andtungsten (W).

[0102] Accordingly, the above description and drawings are only to beconsidered illustrative of exemplary embodiments which achieve thefeatures and advantages of the present invention. Modification andsubstitutions to specific process conditions and structures can be madewithout departing from the spirit and scope of the present invention.Thus, the invention is not to be considered as being limited by theforegoing description and drawings, but is only limited by the scope ofthe appended claims.

What is claimed as new and desired to be protected by Letters Patent ofthe United States is:
 1. An MIS capacitor comprising: a lower electrodeformed over a semiconductor substrate; a dielectric layer comprisingaluminum oxide formed over said lower electrode; and a metal nitrideupper electrode formed over said dielectric layer.
 2. The MIS capacitorof claim 1, wherein said dielectric layer further comprises a materialincorporated with said aluminum oxide.
 3. The MIS capacitor of claim 2,wherein said material is selected from the group consisting of tantalumoxide, zirconium oxide, hafnium oxide, hafnium-aluminum-oxygen alloysand lanthanum-aluminum-oxygen alloys.
 4. The MIS capacitor of claim 3,wherein said dielectric layer comprises aluminum oxide and tantalumoxide.
 5. The MIS capacitor of claim 3, wherein said dielectric layer isformed of interleaved layers of aluminum oxide and tantalum oxide. 6.The MIS capacitor of claim 1, wherein said dielectric layer comprises analuminum oxide/tantalum oxide/aluminum oxide composite stack.
 7. The MIScapacitor of claim 1, wherein said dielectric layer consists essentiallyof an aluminum oxide dielectric layer.
 8. The MIS capacitor of claim 1,wherein said dielectric layer is an ALD aluminum oxide layer.
 9. The MIScapacitor of claim 8, wherein said dielectric layer is an annealed ALDaluminum oxide layer.
 10. The MIS capacitor of claim 8, wherein said ALDaluminum oxide layer has a thickness of about 10 Angstroms to about 100Angstroms.
 11. The MIS capacitor of claim 1, wherein said upperelectrode is a tungsten nitride layer.
 12. The MIS capacitor of claim11, wherein said upper electrode is an ALD tungsten nitride layer. 13.The MIS capacitor of claim 12, wherein said ALD tungsten nitride layeris a nitridized ALD tungsten nitride layer.
 14. The MIS capacitor ofclaim 1, wherein said upper electrode is a titanium nitride layer. 15.The MIS capacitor of claim 14, wherein said upper electrode is an ALDtitanium nitride layer.
 16. The MIS capacitor of claim 15, wherein saidALD titanium nitride layer is a nitridized ALD titanium nitride layer.17. The MIS capacitor of claim 1, wherein said upper electrode is aboron-doped titanium nitride layer.
 18. The MIS capacitor of claim 17,wherein said boron-doped titanium nitride layer is a nitridizedboron-doped titanium nitride layer.
 19. The MIS capacitor of claim 18,wherein said boron-doped titanium nitride layer has a boronconcentration of about 0.01% to about 30%.
 20. The MIS capacitor ofclaim 1, wherein said lower electrode is formed of a material selectedfrom the group consisting of hemispherical grained polysilicon, silica,germanium and silicon.
 21. The MIS capacitor of claim 20, wherein saidlower electrode is formed of hemispherical grained polysilicon.
 22. TheMIS capacitor of claim 21, wherein said lower electrode is formed ofetched hemispherical grained polysilicon with activated hemisphericalgrained polysilicon grains.
 23. The MIS capacitor of claim 22, whereinsaid etched hemispherical grained polysilicon is a nitridized etchedhemispherical grained polysilicon.
 24. The MIS capacitor of claim 22,wherein said etched hemispherical grained polysilicon is an annealedhemispherical grained polysilicon.
 25. The MIS capacitor of claim 1further comprising a silicon-doped layer at the interface between saidlower electrode and said dielectric layer comprising aluminum oxide. 26.The MIS capacitor of claim 25, wherein said silicon-doped layer has athickness of about 5 Angstroms to about 50 Angstroms.
 27. The MIScapacitor of claim 25, wherein said silicon-doped layer is analuminum-oxygen-silicon layer.
 28. The MIS capacitor of claim 1 furthercomprising a metal-doped layer at the interface between said dielectriclayer comprising aluminum oxide and said metal nitride upper electrode.29. The MIS capacitor of claim 28, wherein said metal-doped layer has athickness of about 5 Angstroms to about 100 Angstroms.
 30. The MIScapacitor of claim 28, wherein said metal-doped layer is analuminum-titanium-oxygen-nitrogen layer.
 31. The MIS capacitor of claim28, wherein said metal-doped layer comprises a metal similar to themetal of said metal nitride upper electrode.
 32. A memory devicecomprising: a substrate; a memory cell formed over said substrate, saidmemory cell comprising a transistor including a gate fabricated on saidsubstrate, and source and drain regions in said substrate disposedadjacent to said gate; and a charge storage capacitor electricallyconnected to one of said source and drain regions, said capacitorcomprising a semiconductive layer, an aluminum oxide dielectric layerformed over said semiconductive layer, and a metal nitride layer formedover said aluminum oxide dielectric layer.
 33. The memory device ofclaim 32, wherein said aluminum oxide dielectric layer further comprisesa material incorporated with said aluminum oxide.
 34. The memory deviceof claim 33, wherein said material is selected from the group consistingof tantalum oxide, zirconium oxide, hafnium oxide,hafnium-aluminum-oxygen alloys and lanthanum-aluminum-oxygen alloys. 35.The memory device of claim 33, wherein said aluminum oxide dielectriclayer further comprises tantalum oxide.
 36. The memory device of claim33, wherein said aluminum oxide dielectric layer is formed ofinterleaved layers of aluminum oxide and tantalum oxide.
 37. The memorydevice of claim 33, wherein said aluminum oxide dielectric layer is anALD aluminum oxide layer.
 38. The memory device of claim 37, whereinsaid aluminum oxide dielectric layer is an annealed ALD aluminum oxidelayer.
 39. The memory device of claim 37, wherein said ALD aluminumoxide layer has a thickness of about 10 Angstroms to about 100Angstroms.
 40. The memory device of claim 32, wherein said metal nitridelayer is a tungsten nitride layer.
 41. The memory device of claim 40,wherein said metal nitride layer is an ALD tungsten nitride layer. 42.The memory device of claim 41, wherein said ALD tungsten nitride layeris a nitridized ALD tungsten nitride layer.
 43. The memory device ofclaim 32, wherein said metal nitride layer is a titanium nitride layer.44. The memory device of claim 43, wherein said metal nitride layer isan ALD titanium nitride layer.
 45. The memory device of claim 44,wherein said ALD titanium nitride layer is a nitridized ALD titaniumnitride layer.
 46. The memory device of claim 32, wherein said metalnitride layer is a boron-doped titanium nitride layer.
 47. The memorydevice of claim 46, wherein said boron-doped titanium nitride layer is anitridized boron-doped titanium nitride layer.
 48. The memory device ofclaim 47, wherein said boron-doped titanium nitride layer has a boronconcentration of about 0.01% to about 30%.
 49. The memory device ofclaim 32, wherein said semiconductive layer is formed of a materialselected from the group consisting of hemispherical grained polysilicon,silica, germanium and silicon.
 50. The memory device of claim 49,wherein said semiconductive layer is formed of hemispherical grainedpolysilicon.
 51. The memory device of claim 50, wherein saidsemiconductive layer is formed of etched hemispherical grainedpolysilicon with activated hemispherical grained polysilicon grains. 52.The memory device of claim 51, wherein said etched hemispherical grainedpolysilicon is a nitridized etched hemispherical grained polysilicon.53. The memory device of claim 51, wherein said etched hemisphericalgrained polysilicon is an annealed hemispherical grained polysilicon.54. The memory device of claim 32, wherein said memory cell is a DRAMmemory cell.
 55. The memory device of claim 32, wherein said memory cellis a SRAM memory cell.
 56. A processor-based system comprising: aprocessor; and an integrated circuit coupled to said processor, at leastone of said integrated circuit and processor containing a capacitor,said capacitor comprising a hemispherical grained polysilicon lowercapacitor electrode; an aluminum oxide dielectric layer formed over saidlower capacitor electrode; and a metal nitride upper capacitor electrodeformed over said aluminum oxide dielectric layer.
 57. Theprocessor-based system of claim 56, wherein said hemispherical grainedpolysilicon lower electrode is a nitridized hemispherical grainedpolysilicon lower electrode.
 58. The processor-based system of claim 56,wherein said aluminum oxide dielectric layer is an ALD aluminum oxidedielectric layer.
 59. The processor-based system of claim 58, whereinsaid aluminum oxide dielectric layer is a nitridized ALD aluminum oxidedielectric layer.
 60. The processor-based system of claim 56, whereinsaid aluminum oxide dielectric layer further comprises a materialincorporated with said aluminum oxide.
 61. The processor-based system ofclaim 60, wherein said material is selected from the group consisting oftantalum oxide, zirconium oxide, hafnium oxide, hafnium-aluminum-oxygenalloys and lanthanum-aluminum-oxygen alloys.
 62. The processor-basedsystem of claim 56, wherein said integrated circuit is a memory device.63. The processor-based system of claim 62, wherein said memory deviceis a DRAM memory device.
 64. The processor-based system of claim 62,wherein said memory device is a SRAM memory device.
 65. A method offorming an MIS capacitor on a semiconductor substrate, comprising theacts of: forming a semiconductive layer over a substrate; forming adielectric layer comprising aluminum oxide over said semiconductivelayer by atomic layer deposition; and forming a metal nitride layer oversaid dielectric layer.
 66. The method of claim 65, wherein saidsemiconductive layer is formed of hemispherical grained polysilicon. 67.The method of claim 66 further comprising the act of opening the grainswhich form said layer of hemispherical grained polysilicon to activatesaid grains.
 68. The method of claim 67, wherein said act of openingsaid grains further comprising etching said layer of hemisphericalgrained polysilicon to form an etched layer of hemispherical grainedpolysilicon.
 69. The method of claim 69, wherein said act of etchingsaid layer of hemispherical grained polysilicon further comprisescontacting said layer of hemispherical grained polysilicon with asolution of HF.
 70. The method of claim 69 further comprising the act ofsubjecting said layer of hemispherical grained polysilicon to an RTNprocess.
 71. The method of claim 69 further comprising the act ofsubjecting said layer of hemispherical grained polysilicon to an annealprocess.
 72. The method of claim 69 further comprising the act ofsubjecting said layer of hemispherical grained polysilicon to a PH₃anneal.
 73. The method of claim 65, wherein said metal nitride layer isa titanium nitride layer formed by CVD.
 74. The method of claim 65,wherein said metal nitride layer is a titanium nitride layer formed byALD.
 75. The method of claim 74, wherein said titanium nitride layer isformed by ALD using a nitrogen source and a titanium source precursor.76. The method of claim 65, wherein said metal nitride layer is aboron-doped titanium nitride layer formed by CVD.
 77. The method ofclaim 77, wherein said act of providing said boron-doped titaniumnitride layer further comprises the act of incorporating boron into atitanium nitride layer.
 78. The method of claim 78, wherein said act ofincorporating boron into a titanium nitride layer further comprises theact of exposing said titanium nitride layer to B₂H₆.
 79. The method ofclaim 79, wherein said act of incorporating boron into a titaniumnitride layer further comprises the act of exposing said titaniumnitride layer to B₂H₆ at a temperature of about 200° C. to about 600° C.80. The method of claim 65, wherein said metal nitride layer is atungsten nitride layer formed by CVD.
 81. The method of claim 65,wherein said metal nitride layer is a tungsten nitride layer formed byALD.
 82. The method of claim 65, wherein said metal nitride layer is aboron-doped tungsten nitride layer formed by CVD.
 83. The method ofclaim 82, wherein said act of providing said boron-doped tungstennitride layer further comprises the act of incorporating boron into atungsten nitride layer.
 84. The method of claim 65, wherein saidaluminum oxide dielectric layer is formed by ALD using an ozone sourceand an aluminum source precursor.
 85. The method of claim 86, whereinsaid aluminum source precursor is trimethyl-aluminum.
 86. The method ofclaim 65, wherein said aluminum oxide dielectric layer is formed to athickness of about 10 Angstroms to about 500 Angstroms.
 87. The methodof claim 86, wherein said aluminum oxide dielectric layer is formed to athickness of about 25 Angstroms to about 100 Angstroms.
 88. The methodof claim 65, wherein said aluminum oxide dielectric layer furthercomprises a material selected from the group consisting of tantalumoxide, zirconium oxide, hafnium oxide, hafnium-aluminum-oxygen alloysand lanthanum-aluminum-oxygen alloys.
 89. The method of claim 88,wherein said aluminum oxide dielectric layer is formed as a compositestack of at least one aluminum oxide layer and at least one tantalumoxide layer.
 90. The method of claim 89, wherein said aluminum oxidedielectric layer is formed of interleaved layers of aluminum oxide andtantalum oxide.
 91. The method of claim 90, wherein said aluminum oxidedielectric layer is an aluminum oxide/tantalum oxide/aluminum oxidestack.
 92. A method of forming an aluminum oxide MIS capacitor on asemiconductor substrate, comprising the acts of: forming a lowercapacitor electrode of hemispherical grained polysilicon over saidsemiconductor substrate; forming a dielectric composite stack comprisingaluminum oxide over said lower capacitor electrode; and forming an uppercapacitor electrode of tungsten nitride over said dielectric compositestack.
 93. The method of claim 92, wherein said dielectric compositestack is formed by ALD.
 94. The method of claim 93, wherein saiddielectric composite stack is formed of interleaved layers of aluminumoxide and another metal oxide material.
 95. The method of claim 94,wherein said metal oxide material is selected from the group consistingof tantalum oxide, zirconium oxide, hafnium oxide,hafnium-aluminum-oxygen alloys and lanthanum-aluminum-oxygen alloys. 96.The method of claim 92 further comprising the act of subjecting saiddielectric composite stack to a nitridizing treatment.
 97. The method ofclaim 96 further comprising the act of subjecting said dielectriccomposite stack to a PH₃ anneal treatment.
 98. The method of claim 92,wherein said tungsten nitride layer is formed by ALD using a tungstensource and a nitrogen source precursor.
 99. The method of claim 92further comprising the act of etching said hemispherical grainedpolysilicon to form an etched hemispherical grained polysilicon. 100.The method of claim 99, wherein said act of etching said hemisphericalgrained polysilicon further comprises contacting said hemisphericalgrained polysilicon with a solution of HF.
 101. The method of claim 100further comprising the act of subjecting said hemispherical grainedpolysilicon to a PH₃ anneal.
 102. The method of claim 101 furthercomprising the act of subjecting said hemispherical grained polysiliconto an RTN treatment.
 103. The method of claim 102 further comprising theact of subjecting said hemispherical grained polysilicon to a HFsolution after said PH₃ anneal and before said RTN treatment.